The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
In general, an integrated circuit layout is used to form active regions, contact features and an isolation feature. The isolation feature may be formed between the active regions, and the contact features are formed on the active regions. However, the contact features (adjacent to the isolation feature) may have a poor contact landing on the active regions. This is because the active regions (which are often formed from silicon germanium) have a different growth rate from the isolation feature (which is often formed from oxide). When the active regions are formed using an epitaxy or epitaxial process, the surfaces (or facet) of the active regions (which are adjacent to the isolation feature) are inclined. Therefore, the contact features have poor contact landing on the active regions due to the inclined surfaces. The poor contact landing increases the resistance of the IC and impacts the IC performance and yield.